1. Technical Field
The present invention relates generally to a method and apparatus for monitoring memory addresses, and, more particularly, to a method and apparatus for monitoring memory addresses through a data terminal of memory.
2. Related Art
In general, with regard to the addresses of Synchronous DRAM (SDRAM), a Micro Controller Unit (MCU) converts memory addresses into row and column addresses in order to reduce the number of pins to the highest degree and minimize power consumption.
FIG. 1 is a diagram showing a mapping relationship between the memory and row addresses of a conventional SDRAM and a mapping relationship between the memory and column addresses thereof.
In order to perform write and read operations in association with SDRAM, an MCU converts corresponding memory addresses 106 and 108 into a row address 104 and a column address 102, transmits the row address 104 to memory (not shown), and then transmits the column address 102 to the memory.
Here, the memory addresses 106 and 108 are the actual addresses of data that are required by the MCU, and the row address 104 and the column address 102 are addresses into which the memory addresses 106 and 108 are converted in order to perform write and read operations in association with the SDRAM.
FIG. 2 is a timing diagram when a write command is executed in a conventional SDRAM.
As shown in this drawing, an address ADDR of SDRAM is input with it being divided into a row address RAS_ADDR1 and column addresses CAS_ADDR1 and CAS_ADDR2. When an nRAS signal is at a low voltage level, the row address is reflected, and, when an nCAS signal is at a low voltage level, the column address is reflected. Here, the data pin (DQ pin) of the SDRAM is a port through which actual data is transferred, and nDQM is a signal that determines the operating range of a DQ signal. A one-cycle data write operation is performed during interval ‘1’ (202 of FIG. 2), and a four-cycle data write operation is performed during interval ‘2’ (204 of FIG. 2). Here, one cycle refers to one memory clock.
Furthermore, when the nCAS signal is at a low voltage level and an nWE signal is at a low voltage level, a write operation is performed, and, when the nWE signal is at a high voltage level, a read operation is performed. That is, a write memory command or a read memory command is performed. Consequently, in FIG. 2, the row address RAS_ADDR1 is commonly used, an opration of writing data D1 is performed using the column address CAS_ADDR1, and consecutive operations of writing data D2, D3, D4 and D5 are performed using the column address CAS_ADDR2 after three cycles.
FIG. 3 is a timing diagram when a read command is executed in the conventional SDRAM.
Referring to FIG. 3, when an nCAS signal is at a low voltage level and an nWE signal is at a high voltage level, a read command is executed. In the case where CAS Latency (CL) is set to 2, read data D1 is generated after two cycles. In the case where the CL is set to 3, read data D2, D3, D4 and D5 are generated after three cycles. Consequently, in FIG. 3, a row address RAS_ADDR1 is commonly used, an operation of reading data D1 is performed using a column address CAS_ADDR1, and operations of reading data D2, D3, D4 and D5 are performed using a column address CAS_ADDR2 after three cycles.
However, since the write and read operations shown in FIGS. 2 and 3 are performed by applying the row address and the column addresses to the address pin of the SDRAN, there is a problem in that it is difficult for a user of SDRAM to find actual memory addresses that are used by an MCU in write and read operations.
Furthermore, in order to find actual memory addresses used by an MCU or a data flow from the outside of a chip, SDRAM signals are required to be directly monitored using a logic analyzer, an oscilloscope, or the like. There is difficulty in finding actual addresses because row or column addresses are measured instead of actual memory addresses. Accordingly, there is a problem in that a measurement pin must be further provided in order to directly monitor actual memory addresses.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.